So far, a phase-locked loop circuit (PLL) is used for extracting synchronization signals or clocks in a VTR or a disc reproducing apparatus.
This phase-locked loop is a circuit for producing an output synchronized in phase or frequency with a reference signal. It is a frequency feedback circuit having a phase comparator 251 for comparing the phase relation between two signals and outputting the result of comparison, a low-pass filter for taking out low frequency components of the output of the phase comparator 251 and a voltage-controlled oscillator (VCO) 256 for varying the oscillation frequency responsive to the output of the low-pass filter.
Referring to FIG. 1, a reference signal having a frequency equal to f.sub.in enters an input terminal 258 and thence is supplied to above-described REF input terminal of the phase comparator 251. Also, a VCO output signal from the VCO 256, having a frequency equal to f.sub.VCO, is fed via a frequency dividing circuit 257 to a VER input terminal of the phase comparator 251.
The phase comparator 251 phase-compares the reference signal and an output signal of the frequency dividing circuit 257 to output the results of comparison via a terminal U or a terminal V if the reference signal is advanced in phase or the output signal of the frequency dividing circuit 257 is advanced in phase, respectively.
There are also provided a resistor 252, having its one terminal and its other terminal connected to the terminal U and to the VCO 256, respectively, and a resistor 253 having its one terminal and its other terminal connected to the terminal V and the VCO 256, respectively. There is also provided a resistor 254 having its one terminal connected to output sides of the resistors 252, 253 and to one end of a capacitor 255, the opposite end of which is grounded.
The resistors 252/253, resistor 254 and the capacitor 255 make up the low-pass filter.
This low-pass filter cuts off the high frequency components of the above results of comparison to route the dc components to the VCO 256.
The VCO 256 is responsive to the inputting of the dc component to oscillate and output a signal at the frequency f.sub.VCO, which is set so that f.sub.VCO =f.sub.in .times.N. The oscillation output is routed to an output terminal 259 and to the VCO circuit 257.
The frequency dividing circuit 257 converts the oscillation output with the frequency of f.sub.VCO into a signal with a frequency equal to 1/N, that is into the signal having the frequency of f.sub.in. This signal is fed to the terminal VER of the phase comparator 251.
In the above structure of the phase-locked loop, the VCO output signal is synchronized at all times with the reference signal at a pre-set constant frequency.
There is also known a dedicated IC produced on gate-arraying or integrating with the phase comparator 251 and the VCO 256. This IC is available as a small size device.
The phase comparator 251 is constructed by a combination of logic circuits as shown in FIG. 2. FIG. 3 shows a timing chart of reference data (REF), input data (VER) and other data.
Referring to FIG. 3, ND data are outputted as from the rising of input data up to rising of the next reference data, whilst NU data are outputted as from the rising of the next input data up to rising of the next reference data. The ND data and the NU data are generated and outputted by the phase comparator 251.
Thus, if the phase comparator for outputting the ND data or the NU data are constructed as shown in FIG. 2, there are occasions wherein various loops or feedback loops exist from the input to the output, these loops exhibiting non-symmetrical delays in the IC.
For example, the one input terminal of the OR gate 203 of the first stage is directly fed with the reference signal from a REF input terminal 201, while its opposite side input terminal is fed with, for example, an output from an inverter 213. Between these two signals, there is produced a difference in delay of at least three stages.
Thus, in many cases, the delays of two signals entering the logic circuits differ from each other. This differential delay is responsible for generation of so-called whiskers in the NU data or ND data in the timing chart of FIG. 3, thus tending to produce malfunctions of the PLL circuit in its entirety.
Although interconnections may be designed in consideration of the above delays, difficulties are encountered especially in interconnection management in a gate array circuit.
In view of the above-described status of the art, it is an object of the present invention to provide a phase-locked loop circuit which is simpler in structure and which is insusceptible to malfunctions of the entire circuit.